1. Field of the Invention
This invention relates to a multilayer wiring substrate structure in which wiring patterns formed on respective layers of a multilayer wiring substrate are connected through a via, and more specifically, it relates to a multilayer wiring substrate structure in which high speed signals are transmitted through wiring patterns of a multilayer wiring substrate.
2. Description of the Related Art
In recent years, along with an increase in data transmission amount, a bandwidth beyond the Gbps level has been spread for realization of a higher speed of devices and high speed signal transmission. A wiring pattern formed on a printed-wiring substrate (hereinafter referred to as PWB) is used in common as a transmission path in a transmission apparatus and a system. Also, in order to ensure a transmission quality of the high speed signal wiring, various design methods are adopted for the device and the PWB.
For example, as the design method for the device, a method of adopting a device having a built-in function of a pre-emphasis, an equalizer, an OCD (Off Chip Driver), or an ODT (On Die Termination) is conceivable. Also, possible examples of the design method for the PWB include an decrease in dielectric loss and resistance loss by adopting a base material for a high frequency (a low dielectric loss tangent (tan δ), low dielectric constant (∈r), VLP (Very Low Profile) copper foil, a characteristic impedance matching, and an achievement of suppression in reflection and transmission loss (signal attenuation) by eliminating a branch of a VIA (an unnecessary part for signal transmission in the VIA) through an IVH (Interstitial Via Hole), build-up, or the like. It should be noted that in the following description, a length necessary for the signal transmission in the via is referred to as backbone length and a length of the via stab which is the unnecessary part for the signal transmission in the via is referred to as branch length.
Here, the reflection and the transmission loss due to the via stab are examined. First, regarding the reflection due to the via stab, the characteristic impedance is discontinuously generated due to the via stab and reflectivity coefficient and transmission coefficient are not 0, so that reflected waves are generated.
In addition, regarding the transmission loss due to the via stab, by varying various parameters such as a bit rate (reduction of an operation frequency), a characteristic impedance which depends on a thickness of the copper foil and a width of the wiring in the wiring pattern, a dielectric constant of the base material for the PWB, and an interlayer distance between adjacent wiring patterns, a property value of a raw material for the base material such as the dielectric loss tangent and the dielectric constant, a physical line length (a shape of a via stab depend on the backbone length and the branch length), and the like, the transmission loss (the signal attenuation) is determined.
This bit rate is determined as a specification for satisfying a condition for a targeted circuit operation in many cases, and it is basically impossible to change the bit rate. In particular, the demanded specification cannot be satisfied in the future, in a case where the specification of a set value of the bit rate is increased, as a dependence property of the frequency exists in the transmission loss, if a countermeasure for the transmission loss is not conducted through other parameters.
As the characteristic impedance depends on the property value of the substrate material which directly relates to a cost, although it is a principle way to design a matching circuit, the characteristic impedance can be realized by adjusting the respective physical parameters. Thus, the control is relatively easy.
In addition, the property value is determined in a trade-off relation with respect to the usage of a raw material having a more satisfactory characteristic for the base material.
Furthermore, regarding the via stab, the branch length varies depending on which layer the plural writing patterns connected through the via are arranged on. In a case of high density wirings, a freedom in design is lost and it is necessary to determine whether the transmission loss satisfies the permissive spec in consideration of the via stab. In particular, the transmission loss due to the via stab occupies a non-negligible ratio also in the entire wiring paths.
As described above, in order to ensure the transmission quality of the high speed signal wiring, the various design methods are adopted for the device and the PWB. However, if a safer margin is prepared, the countermeasure cost is of course tended to be increased. Thus, in actuality, the countermeasure is selected based on cost-benefit performance.
For this reason, the following convention technologies are proposed as a method of decreasing the branch length due to the interlayer connecting via, which is the non-negligible parameter related to the transmission loss. FIG. 19A is a cross-sectional view for describing a penetration via, FIG. 19B is a cross-sectional view for describing a half-penetration via, FIG. 20A is a cross-sectional view for describing the IVH, FIG. 20B is a cross-sectional view for describing the build-up, FIG. 21A is a cross-sectional view for describing a back drill before the back drill is performed, and FIG. 21B is a cross-sectional view for describing the back drill after the back drill is performed. In FIGS. 19 to 21, wiring patterns 201 straddling a plurality of layers formed on a front layer or an internal layer of a multilayer wiring substrate 200 are connected through a via 202. Also, in FIG. 21, a via stab 202a is still remained.
First, there is a conventional technology for providing a penetration via for interlayer connection as the backbone length of the via 202 between a front surface 200a and a back surface 200b of the multilayer wiring substrate 200 (FIG. 19A) or a half-penetration via obtained by affixing the multilayer wiring substrate on which the penetration via is provided with another multilayer wiring substrate (FIG. 19B).
Second, there is a conventional technology for the IVH (FIG. 20A) and the build-up (FIG. 20B) in which the degree of freedom in design is improved while formation of an insulating layer and a conductor layer is performed through a method of photolithography using a resist and a thin film and forming one layer each and interlayer connection is also performed by one layer each.
Third, there is a conventional technology for eliminating the via stab 202a (FIG. 21) by making a hole 203 by using a drill at a part of the multilayer wiring substrate corresponding to the via stab 202a (hereinafter referred to as back drill).
Fourth, there is a conventional technology for providing two through holes in parallel in a conventional multilayer wiring substrate and removing a part of a power source/ground pattern functioning as a return current path of a pattern connecting therebetween (for instance, refer to Japanese Laid-Open Patent Publication No. 2006-140365).
However, in the conventional penetration via, it is necessary to use the entire length of the via as the backbone length. There is a problem of restriction in terms of design that the wiring pattern on the front surface of the multilayer wiring substrate and the wiring pattern on the back surface need to be connected with each other.
Also, in the conventional half-penetration via, after the via is formed on the multilayer wiring substrate, another multilayer wiring substrate needs to be affixed thereto. In the conventional IVH and build-up, the insulating layer and the conductor layer are formed by one layer each, and also the via needs to be formed on each layer. Thus, the number of manufacturing steps is increased. Therefore, there is a problem of restriction in terms of costs that the manufacturing costs are higher than a normal multilayer wiring substrate in which after layers are laminated, a via for penetrating all the layers is formed correctively by using a drill.
In addition, the technology for removing the via stab through the conventional back drill is a process of scraping the unnecessary via stab and it is thus difficult to completely remove the via stab. If the requirement and condition of the transmission characteristics are severe, it is inappropriate to perform the back drill in view of the characteristics and quality. In particular, for a BWB (Back Wiring Board), there is a problem of difficulty for mechanically scraping a minute via stab used for a BGA (Ball Grid Array) which is mounted on a PCB.
Furthermore, in the conventional multilayer wiring substrate, it is necessary to arrange two through holes with respect to one combination for connecting wiring patterns formed on different layers, which leads to an increase in a mounting area of the through holes. Therefore, there is a problem of restriction in design that the area on which the wiring patterns can be formed is narrowed down by the area on which the through holes arranged.